Google Research has completed the 32-bit Coral NPU architecture and published the full design as open-source hardware, closing a year-long, four-milestone release with a new Matrix Execution Unit. Alongside the finished design, Google released version 1.0 of its open IREE/MLIR compiler, and Synaptics used its Tech Day on October 20 to launch the Astra SR200 series, the first commercial microcontrollers built on the second-generation Coral design.
The announcement, posted on the Google Developers Blog on October 20, is aimed at a specific problem: the edge is split across hundreds of proprietary chip architectures, each with its own toolchain. Google’s answer is a standards-based, ML-first RISC-V design that any chipmaker can adopt royalty-free under the Apache 2.0 licence, so a team can optimise a model once and deploy it across vendors, devices and power budgets.
Coral NPU Milestone 4: A Matrix Engine In A Sub-10 Milliwatt Envelope
The first three milestones, released over the past year, delivered a C-programmable RISC-V scalar front end, an RVV v1.0 vector co-processor and a tightly coupled memory subsystem with floating-point support. Milestone 4 adds the Matrix Execution Unit, built on the RISC-V VME specification in the Zvt family, with a dedicated outer-product multiply-accumulate engine that computes a full 2D tile in a single cycle — 256 MACs per cycle — by reusing weights and activations inside local registers.
Google says the unit is configurable for up to 1 TOPS while targeting an average of 10 milliwatts for inference. That envelope is the point: rather than stopping at keyword spotting or basic motion detection, Google says milliwatt-class devices can run continuous, multimodal workloads, including compact transformer models such as Gemma, real-time voice translation on wearables, spatial audio filtering on hearables and low-latency visual perception on robots. The complete 32-bit RTL is available on GitHub today.
The Coral Compiler v1.0 Takes Models From Framework To Silicon
Hardware was only half of the release. The v1.0 compiler stack, built on IREE and MLIR, takes models from JAX, PyTorch and TensorFlow through standard representations such as StableHLO and TOSA, partitions work between the host CPU and the Coral core, and lowers it to scalar, vector and matrix instructions without hand-written assembly. An open-source MPACT simulator and a reference FPGA design let teams benchmark models and tune chip configurations before any silicon is fabricated.
The approach mirrors the openness Google is pushing elsewhere in its stack: it open-sourced TorchTPU this week so PyTorch runs natively on its TPUs, and Amazon has taken a similar portability line with TorchNeuron, which runs PyTorch code unmodified on its Trainium chips. In each case the pitch is the same — remove the rewrite tax that locks developers to one vendor’s silicon.
Synaptics Astra SR200: The First Commercial Coral Silicon
At Synaptics Tech Day on October 20, Synaptics launched three products built on Coral technology. The Astra SR200 series, taped out and launching this month, integrates second-generation Coral NPU IP including the Milestone 2 vector core to deliver 400 GOPS in an ultra-low-power microcontroller package aimed at battery-powered wearables and industrial sensor nodes. VentureBeat reported the SR200 family as three processors combining the Coral design with Synaptics’ own memory, audio, vision and compute blocks, targeting smart glasses, cameras and industrial sensors.
Synaptics also unveiled the Coralboard SR developer kit, powered by the SR200 series, and said the Coralboard SL — a 1 TOPS board built on the Astra SL2619 processor, previewed in limited edition at Google I/O — is now generally available worldwide through DigiKey. Google is supporting the manufacturing path directly: VeriSilicon is handling design implementation and verification for tape-out readiness, and GlobalFoundries’ 12LP+ FinFET process has, across RTL iterations, accelerated core timing by 70% and cut standard-cell area by up to 15%. Google says a 64-bit Coral architecture and CHERI security support are already on the roadmap.
Why It Matters
The Coral NPU matters because it tests whether openness can do for edge silicon what it did for AI frameworks. Edge AI has no equivalent of the converged cloud stack: every wearable, camera and sensor maker picks a proprietary accelerator and inherits its compiler, its quirks and its roadmap. An open RISC-V design with a shared compiler changes the bargaining position of everyone downstream — device makers gain a second source for their AI silicon, model developers gain a stable target that is not one vendor’s product line, and smaller chip firms gain a credible NPU without funding a design team from scratch. The contrast with the closed end of the market, where NVIDIA’s grip on AI compute rests on proprietary GPUs and the CUDA software moat, is deliberate. The open design only becomes a standard, though, if more than one vendor ships it — Synaptics is the first commercial proof, and Google’s own roadmap commitments suggest it intends Coral to be judged on adoption, not on the elegance of the release.
Background
Google introduced the Coral NPU effort last year as an open standard for edge AI, releasing the design in milestones while Synaptics — its first commercial silicon partner, in a collaboration running since January 2025 — built the Astra line around it. The completed architecture, v1.0 compiler and SR200 launch mark the point where Coral stops being a research release and becomes something device makers can buy and ship.
Source: Google Developers Blog; VentureBeat
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